HYBRID SIGNED-DIGIT LOGARITHMIC NUMBER SYSTEM PROCESSOR

被引：9
|
作者：
STOURAITIS, T [1 ]
CHEN, C [1 ]
机构：
[1] OHIO STATE UNIV,DEPT ELECT ENGN,COLUMBUS,OH 43210
来源：
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES | 1993年 / 140卷 / 04期
关键词：
COMPUTER ARITHMETIC; NUMBER SYSTEMS; VLSI;
D O I：
10.1049/ip-e.1993.0030
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor is investigated. Appropriate radices were chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude numbers was developed to enhance the overall design. The hybrid SD/LNS processor exploits the parallelism that is offered by the SD number system to boost the performance of the fast LNS processors, and compares favourably to conventional LNS processor designs.
引用
收藏
页码：205 / 210
页数：6
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