A DIGITAL DIFFERENTIAL-LINE RECEIVER FOR CMOS VLSI CIRCUITS

被引：2
|
作者：
ANGLADA, R
RUBIO, A
机构：
[1] Department of Electronic Engineering, Polytechnical University of Catalunya, 08028 Barcelona
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS | 1991年 / 38卷 / 06期
关键词：
D O I：
10.1109/31.81866
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Interferences due to parasitic capacitances between close circuits may produce undesired logic behaviors in VLSI circuits. A CMOS differential-line receiver is proposed to avoid the effect of these perturbances. The receiver reaches a differential and common mode noise immunity which is higher than the circuit power supply voltage.
引用
收藏
页码：673 / 675
页数：3
相关论文
共 50 条
  • [1] SPURIOUS SIGNALS IN DIGITAL CMOS VLSI CIRCUITS - A PROPAGATION ANALYSIS
    MOLL, F
    RUBIO, A
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (10): : 749 - 752
  • [2] QUIESCENT CURRENT SENSOR CIRCUITS IN DIGITAL VLSI CMOS TESTING
    RUBIO, A
    FIGUERAS, J
    SEGURA, J
    [J]. ELECTRONICS LETTERS, 1990, 26 (15) : 1204 - 1206
  • [3] DELAY OPTIMIZATION OF DIGITAL CMOS VLSI CIRCUITS BY TRANSISTOR REORDERING
    CARLSON, BS
    LEE, SJ
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (10) : 1183 - 1192
  • [4] CMOS sensors for on-line thermal monitoring of VLSI circuits
    Szekely, V
    Marta, C
    Kohari, Z
    Rencz, M
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1997, 5 (03) : 270 - 276
  • [5] Analysis and design of PTAT temperature sensor in digital CMOS VLSI circuits
    Golda, A.
    Kos, A.
    [J]. PROCEEDINGS OF THE INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, : 415 - +
  • [6] A crosstalk sensor implementation for measuring interferences in digital CMOS VLSI circuits
    Sainz, JA
    Roca, M
    Muñoz, R
    Maiz, JA
    Aguado, LA
    [J]. 6TH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, PROCEEDINGS, 2000, : 45 - 51
  • [7] Evaluating and improving transient error tolerance of CMOS digital VLSI circuits
    Zhao, Chong
    Dey, Sujit
    [J]. 2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2006, : 814 - +
  • [8] AN APPROACH TO CROSSTALK EFFECT ANALYSIS AND AVOIDANCE TECHNIQUES IN DIGITAL CMOS VLSI CIRCUITS
    ANGLADA, R
    RUBIO, A
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 1988, 65 (01) : 9 - 17
  • [9] FAULT SIMULATION IN CMOS VLSI CIRCUITS
    ZAGHLOUL, ME
    GOBOVIC, D
    [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1991, 138 (04): : 203 - 212
  • [10] EFFICIENT TESTS FOR CMOS VLSI CIRCUITS
    RADHAKRISHNAN, D
    LAI, CM
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 1991, 71 (01) : 29 - 43
12345