共 50 条
- [31] FAULT LOCATION IN LOGIC-CIRCUITS BASED ON THE MAJORITY PROPERTIES OF SOME FAILURES [J]. AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1980, (06): : 72 - 74
- [32] APPLICATION OF FAULT FOLDING IN TEST-GENERATION FOR LOGIC-CIRCUITS - REPLY [J]. DIGITAL PROCESSES, 1980, 6 (01): : 109 - 109
- [33] Stuck-at-fault testing for quasi-delay-insensitive logic circuits [J]. Syst Comput Jpn, 2 (19-27):
- [34] AN ALGORITHM FOR THE PARTITIONING OF LOGIC-CIRCUITS [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1984, 131 (04): : 113 - 118
- [35] RELIABLE SYNTHESIS OF LOGIC-CIRCUITS [J]. CYBERNETICS AND SYSTEMS ANALYSIS, 1992, 28 (03) : 472 - 476
- [36] APPLICATION OF FAULT FOLDING IN TEST-GENERATION FOR LOGIC-CIRCUITS - COMMENTS [J]. DIGITAL PROCESSES, 1980, 6 (01): : 105 - 109
- [37] STATISTICAL FAULT-DETECTION IN LOGIC-CIRCUITS WITH NONSTATIONARY INPUT ACTIONS [J]. AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1977, (06): : 45 - 49
- [38] MACROMODELING OF JOSEPHSON LOGIC-CIRCUITS [J]. IEEE TRANSACTIONS ON MAGNETICS, 1983, 19 (03) : 1217 - 1220