PARALLEL IN SEQUENCE - TOWARDS THE ARCHITECTURE OF AN ELEMENTARY CORTICAL PROCESSOR

被引:0
|
作者
KOERNER, E
TSUDA, I
SHIMIZU, H
机构
[1] RES DEV CORP JAPAN,BIOHOLON RES PROJECT,BUNKYO KU,TOKYO 112,JAPAN
[2] UNIV TOKYO,FAC PHARMACEUT SCI,DEPT BIOPHYS,ANAT 2,TOKYO 113,JAPAN
关键词
D O I
暂无
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
引用
收藏
页码:37 / 47
页数:11
相关论文
共 50 条
  • [1] CONTROL OF SENSORY PROCESSING - A HYPOTHESIS ON AND SIMULATION OF THE ARCHITECTURE OF AN ELEMENTARY CORTICAL PROCESSOR
    KOERNER, E
    GROSS, M
    RICHTER, A
    SHIMIZU, H
    LECTURE NOTES IN COMPUTER SCIENCE, 1989, 342 : 291 - 297
  • [2] PARALLEL ARCHITECTURE AND HARDWARE IMPLEMENTATION OF PRE-PROCESSOR AND POST-PROCESSOR FOR SEQUENCE ASSEMBLY
    Kuo, Yuan-Hsiang
    Liu, Chun-Shen
    Li, Yu-Cheng
    Lu, Yi-Chang
    2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2013, : 1158 - 1161
  • [3] A parallel processor architecture for prefetching
    Kim, SM
    Manoharan, S
    I-SPAN 2000: INTERNATIONAL SYMPOSIUM ON PARALLEL ARCHITECTURES ALGORITHMS AND NETWORKS, PROCEEDINGS, 2000, : 254 - 259
  • [4] Parallel multithreaded architecture - a new processor architecture
    Xiaoxing Weixing Jisuanji Xitong, 12 (8-13):
  • [5] Parallel memory architecture for TTA processor
    Tanskanen, Jarno K.
    Pitkanen, Teemu
    Makinen, Risto
    Takala, Jarmo
    EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION - PROCEEDINGS, 2007, 4599 : 273 - +
  • [6] A reconfigurable parallel architecture for a fuzzy processor
    Ascia, G
    Catania, V
    Puliafito, A
    Vita, L
    INFORMATION SCIENCES, 1996, 88 (1-4) : 299 - 315
  • [7] Parallel architecture FFT/IFFT processor
    Wan, Hong-Xing
    Chen, He
    Han, Yue-Qiu
    Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology, 2006, 26 (04): : 338 - 341
  • [8] EPS - AN ELEMENTARY PROGRAMMING SYSTEM FOR THE DELFT PARALLEL PROCESSOR
    DEBRUIJN, MA
    PARALLEL COMPUTING, 1987, 5 (03) : 323 - 337
  • [9] A parallel architecture for VLSI implementation of FFT processor
    Peng, YJ
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 748 - 751
  • [10] MASSIVELY PARALLEL PROCESSOR: ARCHITECTURE AND APPLICATION.
    Dorband, John E.
    The Journal of Forth application and research, 1987, 5 (01):