A reconfigurable parallel architecture for a fuzzy processor

The spread of applications developed using fuzzy logic has stimulated research in the field of hardware architectures to provide adequate support for soft computing. The paper presents the design of a VLSI fuzzy processor whose main features are parallelism and reconfigurability. The former allows fuzzy inferences to be processed parallelly, with a significant increase in speed. The latter allows hardware resources to be configured according to the processing requirements for the applications. The architecture proposed was modelled in VHDL, simulated and synthesized with a target technology of 0.7 mu m. The results in terms of speed and area occupied are presented.