Delay model for dynamically switching coupled on-chip interconnects

Purpose - The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance-inductance-capacitance (RLC) interconnects. Design/methodology/approach - With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in-phase and out of phase switching of lines. Findings - It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent. Originality/value - The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.