PAGE MODE PROGRAMMING 1MB CMOS EPROM

被引：0
|
作者：
HAGIWARA, T
MATSUO, H
FUKUDA, M
MATSUNO, Y
FURUNO, T
KURODA, K
YASUI, T
KATTO, H
SHIMIZU, A
机构：
[1] HITACHI MUSASHI WORKS,KODAIRA,TOKYO,JAPAN
[2] HITACHI VLSI ENGN,KOKUBUNJI,TOKYO,JAPAN
来源：
ISSCC DIGEST OF TECHNICAL PAPERS | 1985年 / 28卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：174 / 175
页数：2
相关论文
共 50 条
  • [1] A 1MB EPROM
    OKUMURA, K
    OHYA, S
    YAMAMOTO, M
    WATANABE, T
    SHIMAMURA, Y
    KIKUCHI, M
    ISSCC DIGEST OF TECHNICAL PAPERS, 1984, 27 : 140 - 141
  • [2] A PROGRAMMABLE 80NS 1MB CMOS EPROM
    SAITO, S
    TANAKA, S
    ATSUMI, S
    YOSHIKAWA, K
    SATO, M
    MAKITA, K
    MORI, S
    NOZAWA, H
    IIZUKA, T
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 176 - 177
  • [3] A 1MB CMOS DRAM WITH FAST PAGE AND STATIC COLUMN MODES
    SAITO, S
    FUJII, S
    OKADA, Y
    SAWADA, S
    SHINOZAKI, S
    NATORI, K
    OZAWA, O
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 252 - 252
  • [4] A 1MB CMOS DRAM
    KIRSCH, HC
    CLEMONS, DG
    DAVAR, S
    HARMAN, JE
    HOLDER, CH
    HUNSICKER, WF
    PROCYK, FJ
    STEFANY, JH
    YANEY, DS
    PETRIZZI, JB
    IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, 1985, 28 : 256 - 257
  • [5] Logic design of special reading and writing method for 1MB EPROM
    Zhiren, Zhou
    Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 1994, 21 (02):
  • [6] A 1MB CMOS DRAM WITH A DIVIDED BITLINE MATRIX ARCHITECTURE
    TAYLOR, R
    JOHNSON, M
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 242 - 243
  • [7] A 29NS 1MB CMOS MASK ROM
    LIN, JM
    KEN, MWD
    TUAN, HC
    KUNG, CH
    LIAO, IC
    TSENG, KS
    LIN, JJ
    1989 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS: PROCEEDINGS OF TECHNICAL PAPERS, 1989, : 36 - 40
  • [8] A 16-NS 1-MB CMOS EPROM
    KURIYAMA, M
    ATSUMI, S
    IMAMIYA, KI
    IYAMA, Y
    MATSUKAWA, N
    ARAKI, H
    NARITA, K
    MASUDA, K
    TANAKA, S
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) : 1141 - 1146
  • [9] AN EXPERIMENTAL 80NS 1MB DRAM WITH FAST PAGE OPERATION
    KALTER, HL
    COPPENS, P
    ELLIS, W
    FIFIELD, J
    KOKOSZKA, D
    LEASURE, T
    MILLER, C
    NGUYEN, Q
    PAPRITZ, R
    PATTON, C
    POPLAWSKI, M
    TOMASHOT, S
    VANDERHOEVEN, V
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 248 - 249
  • [10] A 20NS STATIC COLUMN 1MB DRAM IN CMOS TECHNOLOGY
    SATO, K
    KAWAMOTO, H
    YANAGISAWA, K
    MATSUMOTO, T
    SHIMIZU, S
    HORI, R
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 254 - 255
12345