ENERGY MINIMIZATION AND DESIGN FOR TESTABILITY

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault in K-bounded circuits. Such circuits may only contain logic blocks with no more than K input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graph G with a vertex for each gate and an edge between a pair of vertices whenever die corresponding gates have a connection. For a (k, K)-circuit, G is a subgraph of a k-tree, which, by definition, cannot have a clique of size greater than k + 1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara's K-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time algorithm minimizes the energy function by recursively eliminating the variables.