THE PERFORMANCE OF THE ALL-DIGITAL DATA TRANSITION TRACKING LOOP USING NONLINEAR-ANALYSIS

被引：10
|
作者：
MILEANT, A
MILLION, S
HINEDI, S
CHENG, U
机构：
[1] Jet Propulsion Laboratory, California Institute of Technology
来源：
IEEE TRANSACTIONS ON COMMUNICATIONS | 1995年 / 43卷 / 2-4期
关键词：
D O I：
10.1109/26.380153
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes the performance of the all-digital data transition tracking loop (DTTL) with coherent and noncoherent sampling using nonlinear theory. The effects of few samples per symbol and of non-commensurate sampling symbol rates are addressed and analyzed for perfectly square pulses as well as Altered pulses. Their impact on the probability density and variance of the phase error are quantified through computer simulations. It is shown that the performance of the all-digital DTTL approaches its analog counterpart when the sampling and symbol rates are noncommensurate (i.e., the number of samples per symbol is irrational). The phase error variance for an even number of samples per symbol is also shown to degrade compared to an odd number of samples per symbol.
引用
收藏
页码：1202 / 1215
页数：14
相关论文
共 50 条
  • [11] Loop Latency Reduction Technique for All-Digital Clock and Data Recovery Circuits
    Chen, I-Fong
    Yang, Rong-Jyi
    Liu, Shen-Iuan
    [J]. 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2009, : 309 - 312
  • [12] Analysis and measurement of spurious emission and phase noise performance of an RF All-Digital Phase Locked Loop using a Frequency Discriminator
    Wicpalek, C.
    Mayer, T.
    Maurer, L.
    Vollenbruch, U.
    Liu, Y.
    Springer, A.
    [J]. 2007 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-6, 2007, : 2196 - +
  • [13] A Low-Jitter All-Digital Phase-Locked Loop Using a Suppressive Digital Loop Filter
    Hsu, Hsuan-Jung
    Huang, Shi-Yu
    [J]. 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 158 - 161
  • [14] All-digital phase locked loop for clock recovery
    Wei, H
    Cheng, T
    [J]. ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 3, 2005, : 395 - 398
  • [15] All-Digital Phase Locked Loop Design Assistant
    Balcioglu, Yalcin
    Dundar, Gunhan
    [J]. 2015 INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD), 2015,
  • [16] WIDEBAND ALL-DIGITAL PHASE-LOCKED LOOP
    YAMAMOTO, H
    MORI, S
    [J]. ELECTRONICS & COMMUNICATIONS IN JAPAN, 1975, 58 (03): : 27 - 34
  • [17] The true performance of the simplified data transition tracking loop
    Simon, MK
    [J]. IEEE TRANSACTIONS ON COMMUNICATIONS, 2005, 53 (06) : 939 - 944
  • [18] An All-Digital Fast Tracking Switching Converter with a Programmable Order Loop Controller for Envelope Tracking RF Power Amplifiers
    Anabtawi, Nijad
    Ferzli, Rony
    Harmanani, Haidar M.
    [J]. 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1690 - 1693
  • [19] An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection
    Jang, Sungchun
    Kim, Sungwoo
    Chu, Sang-Hyeok
    Jeong, Gyu-Seob
    Kim, Yoonsoo
    Jeong, Deog-Kyoon
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62 (09) : 836 - 840
  • [20] An all-digital data recovery circuit optimization using Matlab/Simulink
    Ahmed, SI
    Kwasniewski, TA
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4485 - 4488
12345