共 50 条
- [41] An Efficient Block Cipher Implementation on Many-Core Graphics Processing Units JOURNAL OF INFORMATION PROCESSING SYSTEMS, 2012, 8 (01): : 159 - 174
- [42] A time and area efficient hardware implementation of the misty1 block cipher Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 794 - 797
- [44] FPGA Implementation of Fast Serial 64-Points FFT/IFFT Block without Reordering Block 2013 INTERNATIONAL CONFERENCE ON INFORMATICS, ELECTRONICS & VISION (ICIEV), 2013,
- [45] A high-performance ASIC implementation of the 64-bit block cipher CAST-128 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1859 - +
- [46] An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation APEC 2005: TWENTIETH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, VOLS 1-3, 2005, : 1412 - 1418
- [48] A High-Speed FPGA Implementation of A Bit-slice Ultra-Lightweight Block Cipher, RECTANGLE 2015 5TH INTERNATIONAL CONFERENCE ON COMPUTER AND KNOWLEDGE ENGINEERING (ICCKE), 2015, : 206 - 211
- [49] Efficient Implementation of Simeck Family Block Cipher on 16-bit MSP430 2017 NINTH INTERNATIONAL CONFERENCE ON UBIQUITOUS AND FUTURE NETWORKS (ICUFN 2017), 2017, : 983 - 988
- [50] New Second-order Threshold Implementation of Sm4 Block Cipher JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2023, 39 (04): : 435 - 445