A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique

被引：2
|
作者：
Fan Mingjun [1 ]
Ren Junyan [1 ,2 ]
Shu Guanghua [1 ]
Guo Yao [3 ]
Li Ning [1 ]
Ye Fan [1 ]
Xu Jun [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China
[2] Fudan Univ, Micro Nanoelect Sci & Technol Innovat Platform, Shanghai 201203, Peoples R China
[3] MediaTek Inc, Beijing 100080, Peoples R China
来源：
JOURNAL OF SEMICONDUCTORS | 2011年 / 32卷 / 01期
基金：
国家高技术研究发展计划(863计划);
关键词：
analog-to-digital converter; opamp-sharing; RC matching; SHA-less; low-power;
D O I：
10.1088/1674-4926/32/1/015002
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
A 12-Bit 40-MS/s pipelined analog-to-digital converter ( ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13-mu m CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noiseand- distortion ratio, and -75.5-dB of total harmonic distortion (the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.
引用
收藏
页数：5
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