EVALUATION OF PROCESS DAMAGE DEPTH USING DISLOCATION-FREE GAAS WAFERS

被引:2
|
作者
YAMAGUCHI, N [1 ]
WATANABE, J [1 ]
机构
[1] NIPPON TELEGRAPH & TEL PUBL CORP, LSI LABS, ATSUGI, KANAGAWA 24301, JAPAN
关键词
D O I
10.1149/1.2087086
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
This paper presents a morphological analysis of GaAs wafer surfaces relating to wafer processes such as slicing, lapping, and polishing. A novel technique using molten KOH etching for determining the depth of deformations caused by processes is described. It was found that the defects caused by the chemimechanical polishing were of the same dimension as the microdefects in the as-grown crystals. Deformation depth due to slicing and lapping were determined by successive polishing and etching until oval pits were the same size as the fine pits caused by residual polishing damage. This depth amounted to 50-70 µm for slicing and 50 µm for lapping. These values are about two times deeper for slicing and three times deeper for lapping than layers where the small cracks and residual damage coexisted as observed by the beveled cross sections. copyright. © 1990, The Electrochemical Society, Inc. All rights reserved.
引用
收藏
页码:2849 / 2853
页数:5
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