Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead

The concept of using a microcontroller coupled to re-programmable FPGAs is being used at the heart of Run-Time Reconfigurable (RTR) systems. This paper presents the development of an RTR system for DSP and telecommunication applications. It differs from other systems, in that it treats reconfiguration time as a key design parameter by employing “design for reconfiguration” where partial reconfiguration is identified in the design of the circuit architecture. Reductions of up to 75% in the implementation time of multiplication, division and square root circuits have been achieved using the Xilinx XC6200 FPGA family. A special hardware/software interface called the Virtual Hardware Handler, has also been developed to support the design approach. It vastly simplifies the reconfiguration operation, reducing it to a simple process of passing pointers and data. The approach has been implemented on a windows-based RTR system.