Design optimization of a CMOS RF detector

A procedure to optimize the design of an RF detector is presented. The optimization enables to minimize the minimum detectable signal (MDS), which is beneficial for maximizing the dynamic range, as it is often desired. The optimization also enables to minimize the bias current consumption. The detector architecture is based on a half-wave MOSFET rectifier and is suitable to implement highly linear envelope detectors. The optimization uses a model based on transistor characteristics extracted from simulations. The model was validated by comparing the predicted MDS to measurements performed at 2 GHz to an RF detector on a 90 nm CMOS process.