Fractures of ultra-low-k material in a chip during a flip-chip process

The low-k/ultra-low-k (LK/ULK) dielectric materials are incorporated in the 40 nm technology node and beyond to reduce resistance and capacitance (RC) delays and improve chip performances. However, the LK/ULK integrity becomes critical in a flip-chip process because of the LK/ULK materials' higher porosity and fragility in mechanics. In this paper, we proposed a three-dimensional (3D) one-level global/local finite element model to study stresses and fracture behaviors in the chip with ULK dielectrics in the heating flip-chip process using SIMULIA ABAQUS software. The global model includes an effective thin layer that is equivalent to Cu/low-k multilayer interconnections. On the basis of stress analysis, the precracks at different locations of back-end of line (BEOL) were introduced to estimate the values of energy release rate (ERR) along the 3D crack fronts and the possible crack extension was discussed. Furthermore, the ERR affected by the ULK modulus, polyimide thickness and copper pillar diameter was investigated. The analysis reveals that the values of ERR are higher in upper layers of the BEOL and their values at interfaces of Cu/ULK are as much as two times than in ULK. The ERR reaches its maximum value under the edge of copper pillar with higher first principal stresses. The crack propagation becomes critical due to a quickly rising value of ERR when the polyimide (PI) thickness or the diameter of copper pillar is decreased. The study helps to understand the fracture behaviors in BEOL of an advanced chip during a packaging process.