Developments of optimum flip-chip bonding process

Flip-chip soldering is the critical technology for solving the current issues of electronic packaging industries that require the high I/O's. In order to increase the manufacturing ability of flip-chip technology, however, yield and reliability issues should overcome. In this study, optimum flip-chip bonding process has been developed by using the test chips that had the electroplated solder bumps. Test chips are composed of three different types that are i) peripheral array pad chip (116 of I/O and 8.25 x 8.25 mm(2)), ii) peripheral array pad chip (196 of I/O and 13.75 x 13.75 mm(2)), and iii) area array pad chip (448 I/O and 11.66 x 11.66 mm(2)) Each test chip has the daisy chain to consider the effect of reliability test. The electrical resistance was measured before and after reliability test. Based on these measurement, failure mode resulted from the moisture absorption was studied using scanning acoustic microscope. To achieve an optimum reflow profile of solder bump, correct temperature profile was set up with respect to the resin base flux. Different bonding forces were tested. Four underfill encapsulants were evaluated for minimum voids that caused the severe defects after reliability test. Also, the gap heights were measured with respect to applied bonding force after underfill was performed. Results from the moisture absorption and thermal cycling were discussed for flip-chip bonding on BT-resin substrates. The test vehicles using flip-chip technology have passed moisture preconditioning and temperature cycling test.