A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology

被引：0
|
作者：
Min-Ki Jeon
Changsik Yoo
机构：
[1] Hanyang University,Integrated Circuits Laboratory, Department of Electronic Engineering
来源：
Analog Integrated Circuits and Signal Processing | 2015年 / 85卷
关键词：
Clock and data recovery (CDR); Phase locked loop (PLL); Digitally-controlled oscillator (DCO);
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A 6-Gbps dual-mode digital clock and data recovery (CDR) circuit for both the mesochronous clocking system and the plesiochronous clocking system has been developed. Fabricated in a 65-nm CMOS technology, the prototype consumes 25.2 and 22.8-mW from 1.2-V supply and root-mean-square jitter of the recovered clock was measured to be 7.2 and 8.5-ps for 6-Gbps mesochronous system and plesiochronous system, respectively. For both operation modes, less than 10−12 bit-error-rate was achieved with 27-1 pseudo-random binary sequence pattern and active area of the implemented CDR circuit is 0.025-mm2.
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页码：209 / 215
页数：6
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