Micro-Task Processing in Heterogeneous Reconfigurable Systems

被引:0
|
作者
Sebastian Wallner
机构
[1] Technical University of Hamburg-Harburg,Department of Distributed Systems
来源
Journal of Computer Science and Technology | 2005年 / 20卷
关键词
system-on-chip; reconfigurable heterogeneous architectures; configuration instructions; descriptors; parallel processing system; signal processing;
D O I
暂无
中图分类号
学科分类号
摘要
New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Configurable System-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.
引用
收藏
页码:624 / 634
页数:10
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