Experimental Evaluation of Reliability of Deep Submicron SOI MOS Transistors at High Temperatures

被引：1
|
作者：
Benediktov A.S. [1 ]
Shelepin N.A. [1 ]
Ignatov P.V. [1 ]
机构：
[1] Molecular Electronics Research Institute (MERI), Zelenograd, Moscow
来源：
Russian Microelectronics | 2018年 / 47卷 / 3期
关键词：
D O I：
10.1134/S1063739718030034
中图分类号：
学科分类号：
摘要：
In this paper, 0.18–0.5 μm SOI MOS transistors are tested for compliance with the reliability criteria applied to high-temperature electronics and their components. The main parameters of SOI MOS transistors are measured in the temperature range from −60 to +300°С. The specific behavior exhibited by SOI MOS transistors at high temperatures should be taken into account when designing high-temperature integrated circuits so as to avoid premature failures and increase the reliability of devices. © 2018, Pleiades Publishing, Ltd.
引用
收藏
页码：217 / 220
页数：3
相关论文
共 50 条
  • [31] Experimental design and evaluation of interconnection materials for improvement of joint reliability at power transistors
    Jansson, P.
    Microelectronics Reliability, 1998, 38 (6-8): : 1297 - 1300
  • [32] Experimental design and evaluation of interconnection materials for improvement of joint reliability at power transistors
    Jansson, P
    MICROELECTRONICS AND RELIABILITY, 1998, 38 (6-8): : 1297 - 1300
  • [33] Evaluation of non-quasi-static effects during SEU in deep-submicron MOS devices and circuits
    Jain, P
    Kumar, DV
    Vasi, JM
    Patil, MB
    19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 188 - 193
  • [34] Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors
    Mohapatra, NR
    Desai, MP
    Narendra, SG
    Rao, VR
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (04) : 959 - 966
  • [35] Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors
    Vescoli, V.
    Park, J. M.
    Enichlmair, H.
    Knaipp, M.
    Roehrer, G.
    Minixhofer, R.
    Schrems, M.
    IET CIRCUITS DEVICES & SYSTEMS, 2008, 2 (03) : 347 - 353
  • [36] Reliability of high-performance monolayer MoS2 transistors on scaled high-κ HfO2
    Lan, Hao-Yu
    Yang, Shao-Heng
    Kantre, Karim-Alexandros
    Cott, Daire
    Tripathi, Rahul
    Appenzeller, Joerg
    Chen, Zhihong
    NPJ 2D MATERIALS AND APPLICATIONS, 2025, 9 (01)
  • [37] A probabilistic-physics-of-failure/short-test approach to reliability assurance for high-performance chips: Models for deep-submicron transistors and optical interconnects
    Haggag, A
    McMahon, W
    Hess, K
    Cheng, K
    Lee, J
    Lyding, J
    2000 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT, 2000, : 179 - 182
  • [38] Evaluation of the High Temperatures Influence on High Frequency C-V Curves of MOS Capacitor
    Borges Ziliotto, Ana Paula
    Bellodi, Marcello
    STATE-OF-THE-ART PROGRAM ON COMPOUND SEMICONDUCTORS 53 (SOTAPOCS 53), 2011, 41 (06): : 163 - 173
  • [39] High-voltage LDMOS transistors fully compatible with a deep-submicron 0.35 μm CMOS process
    Santos, P. M.
    Costa, Vitor
    Gomes, M. C.
    Borges, Beatriz
    Lanca, Mario
    MICROELECTRONICS JOURNAL, 2007, 38 (01) : 35 - 40
  • [40] High reliability sensing circuit for deep submicron spin transfer torque magnetic random access memory
    Kang, Wang
    Zhao, Weisheng
    Klein, J. -O.
    Zhang, Youguang
    Chappert, C.
    Ravelosona, D.
    ELECTRONICS LETTERS, 2013, 49 (20) : 1283 - +
12345