A low-power phase-locked loop for UWB applications

被引：0
|
作者：
Tapio Rapinoja
Kari Stadius
Kari Halonen
机构：
[1] Helsinki University of Technology,Electronic Circuit Design Laboratory
来源：
Analog Integrated Circuits and Signal Processing | 2008年 / 54卷
关键词：
Phase-locked loop; Frequency synthesizer; UWB radio;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.
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页码：95 / 103
页数：8
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