A low jitter and low-power phase-locked loop design

被引：0

作者：

Chen, KH ^{[1
]}

Liao, HS ^{[1
]}

Tzou, LJ ^{[1
]}

机构：

[1] Tamkang Univ, Dept Elect Engn, Taipei, Taiwan

来源：

ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter feature. Novel voltage controlled oscillator (VCO) and phase frequency detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a "three-state" structure with dead zone is 5ps. The power consumption of the proposed DPLL is lower than 6.7mW, and the output-frequency range of the oscillator is from 200MHz to 650MHz. The worst-case cycle jitter is lower than 160ps, and long-term jitter is lower than 220ps. We confirm the results based on 0.5um CMOS technology and 3V supply voltage.

引用

页码：257 / 260

页数：4

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