Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

被引：5
|
作者：
Patrick Girard
Olivier Héron
Serge Pravossoudovitch
Michel Renovell
机构：
[1] Université Montpellier II/CNRS (UMR 5506),Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier
来源：
Journal of Electronic Testing | 2005年 / 21卷
关键词：
FPGA; look-up table (LUT); delay fault; test;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The objective of this paper is to propose a method to test all the delay faults located in Look-Up-Tables (LUTs) of SRAM-based symmetrical FPGAs. This method is developed in a Manufacturing-Oriented Context (MOT). In the first part of the paper, the timing behavior of the LUTs and the physical defects inducing delay faults in the LUTs are analyzed. Then, the detection conditions to test such delay faults are established and requirements on test vectors are derived. Finally a test configuration scheme and its associated test sequence able to test exhaustively the delay faults in all LUTs of a symmetrical FPGA are proposed.
引用
收藏
页码：43 / 55
页数：12
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