Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

被引：5
|
作者：
Patrick Girard
Olivier Héron
Serge Pravossoudovitch
Michel Renovell
机构：
[1] Université Montpellier II/CNRS (UMR 5506),Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier
来源：
Journal of Electronic Testing | 2005年 / 21卷
关键词：
FPGA; look-up table (LUT); delay fault; test;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The objective of this paper is to propose a method to test all the delay faults located in Look-Up-Tables (LUTs) of SRAM-based symmetrical FPGAs. This method is developed in a Manufacturing-Oriented Context (MOT). In the first part of the paper, the timing behavior of the LUTs and the physical defects inducing delay faults in the LUTs are analyzed. Then, the detection conditions to test such delay faults are established and requirements on test vectors are derived. Finally a test configuration scheme and its associated test sequence able to test exhaustively the delay faults in all LUTs of a symmetrical FPGA are proposed.
引用
收藏
页码：43 / 55
页数：12
相关论文
共 50 条
  • [31] On the complexity of universal fault diagnosis for look-up table FPGAs
    Inoue, T
    Miyazaki, S
    Fujiwara, H
    SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 276 - 281
  • [32] HLS-based Fault Tolerance Approach for SRAM-based FPGAs
    Lojda, Jakub
    Podivinsky, Jakub
    Krcma, Martin
    Kotasek, Zdenek
    2016 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2016, : 301 - 302
  • [33] An analysis based on fault injection of hardening techniques for SRAM-based FPGAs
    Sterpone, L.
    Violante, M.
    Rezgui, S.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (04) : 2054 - 2059
  • [34] Exploring Shared SRAM Tables Among NPN Equivalent Large LUTs in SRAM-Based FPGAs
    Asghar, Ali
    Iqbal, Muhammad Mazher
    Ahmed, Waqar
    Ali, Mujahid
    Parvez, Husain
    Rashid, Muhammad
    2016 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2016, : 229 - 232
  • [35] Repeated Look-Up Tables
    Reinhard, Erik
    Garces, Elena
    Stauder, Jurgen
    IEEE TRANSACTIONS ON IMAGE PROCESSING, 2020, 29 : 2370 - 2379
  • [36] Defect and fault tolerance SRAM-based FPGAs by shifting the configuration data
    Doumar, A
    Ito, H
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2000, E83D (05): : 1104 - 1115
  • [37] A Fast Fault Injection Platform of Multiple SEUs for SRAM-Based FPGAs
    Zhang, Rongsheng
    Xiao, Liyi
    Li, Jie
    Cao, Xuebing
    Qi, Chunhua
    Wang, Mingjiang
    2017 PROGNOSTICS AND SYSTEM HEALTH MANAGEMENT CONFERENCE (PHM-HARBIN), 2017, : 213 - 217
  • [38] Evaluation of fault-tolerant designs implemented on SRAM-Based FPGAs
    Asadi, G
    Mirema, SG
    Zarandi, HR
    Ejlali, A
    10TH IEEE PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS, 2004, : 327 - 332
  • [39] A New Fault-Tolerant Architecture for CLBs in SRAM-based FPGAs
    Ben Dhia, Arwa
    Naviner, Lirida
    Matherat, Philippe
    2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2012, : 761 - 764
  • [40] A fast fault injection platform of multiple SEUs for SRAM-based FPGAs
    Zhang, Rongsheng
    Xiao, Liyi
    Li, Jie
    Cao, Xuebing
    Qi, Chunhua
    Li, Jiaqiang
    Wang, Mingjiang
    MICROELECTRONICS RELIABILITY, 2018, 82 : 147 - 152
12345