Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems

The Dynamo system provides a runtime environment for mapping image processing applications to hardware/software platforms that contain a mix of processors and reconfigurable hardware. Dynamo can be used by an image analyst with no knowledge of HW/SW design. The analyst specifies the algorithms implemented in a processing pipeline and the input data. Dynamo dynamically selects the most efficient combination of hardware and software component implementations to minimize pipeline runtime, generates the source code that implements the pipeline, processes the input data using the implementation, and returns the results. We present the design and implementation of Dynamo. Our target domain is image processing pipelines. We chose image processing (IP) because many IP algorithms benefit from acceleration using reconfigurable hardware and many IP applications are structured as a pipeline, where each component can be implemented in software or hardware. Our performance modeling incorporates profiles based on experimental results and on overhead costs. Our results show that modeling of overhead costs is essential to choosing the correct implementation. We illustrate how Dynamo chooses a mix of hardware and software implementations to minimize runtime for several different image processing applications.