Design and evaluation of a hardware/software FPGA-based system for fast image processing

被引：44

作者：

Kalomiros, J. A. ^{[1
]}

Lygouras, J. ^{[2
]}

机构：

[1] Technol & Educ Inst Serres, Dept Informat & Communicat, Terma Magnisias 62100, Serres, Greece

[2] Democritus Univ Thrace, Sect Elect & Informat Syst Technol, Dept Elect & Comp Engn, Polytechn Sch Xanthi, Komotini, Greece

来源：

MICROPROCESSORS AND MICROSYSTEMS | 2008年 / 32卷 / 02期

关键词：

hardware/software co-design; image processing; FPGA; embedded processor;

D O I：

10.1016/j.micpro.2007.09.001

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We evaluate the performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a Field Programmable Gate Array (FPGA) co-processor and a host computer. A LabVIEW (TM) host application controlling a frame grabber and an industrial camera is used to capture and exchange video data with the hardware co-processor via a high speed USB2.0 channel, implemented with a standard macrocell. The FPGA accelerator is based on a Altera Cyclone II chip and is designed as a system-on-a-programmable-chip (SOPC) with the help of an embedded Nios II software processor. The SOPC system integrates the CPU, external and on chip memory, the communication channel and typical image filters appropriate for the evaluation of the system performance. Measured transfer rates over the communication channel and processing times for the implemented hardware/software logic are presented for various frame sizes. A comparison with other solutions is given and a range of applications is also discussed. (c) 2007 Elsevier B.V. All rights reserved.

引用

页码：95 / 106

页数：12

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