Efficient Memory Management for High-Speed ATM Systems

ATM technology placesstrict performance requirements on ATM systems, especially consideringthe scalability of the SDH/SONET physical layerto high speeds. Throughput preservation of the link speed throughprotocols to a higher layer application is a known problem inhigh-speed communication systems. The problem is being addressedwith design methodologies that offer high speed data paths, usingspecialized hardware, and increased processing power, commonlyin the form of embedded processors. In this paper, we presenta case study for a high-speed Queue Manager for ATM systems.The manager enables high-speed data transfer to/fromsystem memory and management of logical data structures (queues).Furthermore, it provides high-speed and importantly, scalabilityand re-usability, so that it can be used in a wide range of ATMsystems, such as workstation adapters, switches, routers, etc.In this work, we provide contributions in two directions. Wedescribe an approach to develop a high-speed, scalable and re-usablememory manager for ATM systems, and then we provide an architectureand implementations in harware as well as in software for embeddedsystems. The results indicate the cost/performancetrade-off's and system scalability and thus, enable designersto choose the implementation that meets their target system requirementswell.