Valley-engineered ultra-thin silicon for high-performance junctionless transistors

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作者
Seung-Yoon Kim
Sung-Yool Choi
Wan Sik Hwang
Byung Jin Cho
机构
[1] School of Electrical Engineering,Department of Materials Engineering
[2] KAIST,undefined
[3] Korea Aerospace University,undefined
来源
Scientific Reports | / 6卷
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摘要
Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineering of the silicon. The strain-induced band splitting and a quantum confinement effect induced from ultra-thin-body silicon are the two main mechanisms for valley engineering. These were obtained from the extremely well-controlled silicon surface roughness and high tensile strain in silicon, thereupon demonstrating a device mobility increase of ~500% in a 2.5 nm thick silicon channel device.
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