Avoiding furnace slip in the era of shallow trench isolation

Although the silicon wafer is strong at room temperature, it is weak at the elevated temperatures necessary for the fabrication of integrated circuits. During thermal processing, a nonuniform elevated temperature produces a nonuniform expansion within the wafer and the resulting lattice forces can cause local or widespread furnace slip. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. Matters are made worse when shallow trench isolation structures are built into the wafer surface. During thermal cycling, the pressure oxide exerts on the silicon side-walls can create dislocations or cause slip-dislocations to move into the device. The causes of furnace slip are examined, and the effects on integrated circuit yield and reliability are reviewed. Characterization methods and the characteristic wafer failure modes are described. The factors that influence the wafer's resistance to furnace slip and the appropriate corrective actions are discussed. A case study is used to describe how shallow trench isolation structures and processing exacerbate the problem of furnace slip.