High throughput compression of double-precision floating-point data

被引:0
|
作者
Burtscher, Martin [1 ]
Ratanaworabhan, Paruj [1 ]
机构
[1] Cornell Univ, Sch Elect & Comp Engn, Ithaca, NY 14853 USA
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes FPC, a lossless compression algorithm for linear streams of 64-bit floating-point data. FPC is designed to compress well while at the same time meeting the high throughput demands of scientific computing environments. On our thirteen datasets, it achieves a substantially higher average compression ratio than BZIP2, DFCM, FSD, GZIP, and PLMI. At comparable compression ratios, it compresses and decompresses 8 to 300 times faster than the otherfive algorithms.
引用
收藏
页码:293 / +
页数:2
相关论文
共 50 条
  • [1] FPC: A High-Speed Compressor for Double-Precision Floating-Point Data
    Burtscher, Martin
    Ratanaworabhan, Paruj
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2009, 58 (01) : 18 - 31
  • [2] A Coprocessor for Double-Precision Floating-Point Matrix Multiplication
    Jia, Xun
    Wu, Guiming
    Xie, Xianghui
    Wu, Dong
    [J]. Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2019, 56 (02): : 410 - 420
  • [3] An analysis of the double-precision floating-point FFT on FPGAs
    Hemmert, KS
    Underwood, KD
    [J]. FCCM 2005: 13TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2005, : 171 - 180
  • [4] An IEEE 754 Double-Precision Floating-Point Multiplier for Denormalized and Normalized Floating-Point Numbers
    Thompson, Ross
    Stine, James E.
    [J]. PROCEEDINGS OF THE ASAP2015 2015 IEEE 26TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2015, : 62 - 63
  • [5] Conversion of Mersenne Twister to double-precision floating-point numbers
    Harase, Shin
    [J]. MATHEMATICS AND COMPUTERS IN SIMULATION, 2019, 161 : 76 - 83
  • [6] Lossless Compression of Double-Precision Floating-Point Data for Numerical Simulations: Highly Parallelizable Algorithms for GPU Computing
    Ohara, Mamoru
    Yamaguchi, Takashi
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2012, E95D (12): : 2778 - 2786
  • [7] Low-Latency Double-Precision Floating-Point Division for FPGAs
    Liebig, Bjoern
    Koch, Andreas
    [J]. PROCEEDINGS OF THE 2014 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2014, : 107 - 114
  • [8] A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier
    Thompson, S. Ross
    Stine, James E.
    [J]. 2020 IEEE 38TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2020), 2020, : 445 - 452
  • [9] VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique
    Manish Kumar Jaiswal
    Ray C. C. Cheung
    [J]. Circuits, Systems, and Signal Processing, 2013, 32 : 15 - 27
  • [10] A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers
    Yun, Juwon
    Lee, Jinyoung
    Chung, Woo-Nam
    Kim, Cheong Ghil
    Park, Woo-Chan
    [J]. IEEE ACCESS, 2020, 8 : 165740 - 165747