A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier

This paper proposes a new algorithm for IEEE 754 Floating point multiplication along with a complete implementation supporting normalized and denormalized numbers. The new rounder is based on injection rounding but instead adds two injections to the intermediate product. The first injection handles the case when the product does not overflow while the second handles the case when it does overflow. A special adder is developed to handle the two injection constants while minimizing duplicated hardware. Dual injection rounding eliminates the complex split between upper and lower bit paths in the single injection rounding algorithm [1] which in turn reduces all three key design targets; delay (1.2%), area (6.4%), and power (7.7%). Our novel design is compared against three designs, a standard injection rounder, Synopsys (R) DesignWare (TM), and Cadence (R) ChipWare (TM).