PAPS: Power budget-Aware Pipeline Scheduling for an Embedded ReRAM-based Accelerator

被引：0
|
作者：
Shuai, Changchi [1 ]
Qiu, Keni [1 ]
机构：
[1] Capital Normal Univ, Beijing, Peoples R China
来源：
SEC'19: PROCEEDINGS OF THE 4TH ACM/IEEE SYMPOSIUM ON EDGE COMPUTING | 2019年
基金：
中国国家自然科学基金;
关键词：
D O I：
10.1145/3318216.3363455
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Many recent works have proposed to embed the emerging resistive switching random-access memory crossbar (ReRAM for short) to an edge device in Internet of Things (IoTs), such that those IoT nodes themselves are smart to process data rather than merely transmit raw data [1]. To acquire high throughput, multiple ReRAMs are scheduled in a pipeline fashion in the execution, but the peak power consumption of the ReRAM pipeline may probably exceed its power budget. Addressing the power issue, this paper proposes a Power budget-Aware Pipeline Scheduling (PAPS) scheme, which can achieve a well balanced and low power ReRAM pipeline.
引用
收藏
页码：352 / 353
页数：2
相关论文
共 50 条
  • [31] ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator
    Song, Zhuoran
    Li, Dongyue
    He, Zhezhi
    Liang, Xiaoyao
    Jiang, Li
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [32] ReCSA: a dedicated sort accelerator using ReRAM-based content addressable memory
    LI Huize
    JIN Hai
    ZHENG Long
    HUANG Yu
    LIAO Xiaofei
    Frontiers of Computer Science, 2023, 17 (02)
  • [33] Multi-Objective Optimization of Deadline and Budget-Aware Workflow Scheduling in Uncertain Clouds
    Calzarossa, Maria Carla
    Della Vedova, Marco L.
    Massari, Luisa
    Nebbione, Giuseppe
    Tessera, Daniele
    IEEE ACCESS, 2021, 9 : 89891 - 89905
  • [34] An efficient ReRAM-based inference accelerator for convolutional neural networks via activation reuse
    Chen, Yan
    Zhang, Jing
    Xu, Yuebing
    Zhang, Yingjie
    Zhang, Renyuan
    Nakashima, Yasuhiko
    IEICE ELECTRONICS EXPRESS, 2019, 16 (18) : 1 - 5
  • [35] FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture
    Ji, Yu
    Zhang, Youyang
    Xie, Xinfeng
    Li, Shuangchen
    Wang, Peiqi
    Hu, Xing
    Zhang, Youhui
    Xie, Yuan
    TWENTY-FOURTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS XXIV), 2019, : 733 - 747
  • [36] ReaDy: A ReRAM-Based Processing-in-Memory Accelerator for Dynamic Graph Convolutional Networks
    Huang, Yu
    Zheng, Long
    Yao, Pengcheng
    Wang, Qinggang
    Liu, Haifeng
    Liao, Xiaofei
    Jin, Hai
    Xue, Jingling
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 41 (11) : 3567 - 3578
  • [37] FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators
    Dhingra, Pratyush
    Ogbogu, Chukwufumnanya
    Joardar, Biresh Kumar
    Doppa, Janardhan Rao
    Kalyanaraman, Ananth
    Pande, Partha Pratim
    2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2024,
  • [38] A Practical Highly Paralleled ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions
    Zhang, Yuhao
    Jia, Zhiping
    Du, Hongchao
    Xue, Runzhen
    Shen, Zhaoyan
    Shao, Zili
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 41 (04) : 922 - 935
  • [39] BATUDE: Budget-Aware Neural Network Compression Based on Tucker Decomposition
    Yin, Miao
    Phan, Huy
    Zang, Xiao
    Liao, Siyu
    Yuan, Bo
    THIRTY-SIXTH AAAI CONFERENCE ON ARTIFICIAL INTELLIGENCE / THIRTY-FOURTH CONFERENCE ON INNOVATIVE APPLICATIONS OF ARTIFICIAL INTELLIGENCE / TWELVETH SYMPOSIUM ON EDUCATIONAL ADVANCES IN ARTIFICIAL INTELLIGENCE, 2022, : 8874 - 8882
  • [40] A ReRAM-Based Convolutional Neural Network Accelerator Using the Analog Layer Normalization Technique
    Gi, Sang-Gyun
    Lee, Hyunkeun
    Jang, Jingon
    Lee, Byung-Geun
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2023, 70 (06) : 6442 - 6451
12345