Embedded chip build-up in a wafer-level packaging environment

Embedded Chip Build-Up technology maintains compatibility with both printed circuit panel and wafer-level packaging infrastructures. In this paper the authors present a detailed infrastructure and cost trade off analysis of embedded chip packaging of microprocessors in these two environments. Packaging cost reported consists of the following elements: Dielectric, Metallization, Patterning, Via Formation, Assembly and other cost additions. The analysis identifies two distinct sources of yield loss: defective chips and build-up interconnect fabrication defects. While the losses due to defective chips remain independent of the packaging environment, build-up interconnect yield losses are strongly influenced by the type of equipment employed as well as the feature sizes of the design.