An analog CMOS rank-order extractor with O(N) complexity using maximum/winner-take-all circuit

被引：0
|
作者：
Hung, YC [1 ]
Liu, BD [1 ]
机构：
[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan
来源：
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Design of a new analog rank-order extractor with input expandable capability is described. An extraction for rth rank order is defined that identifying the rth largest magnitude of input variables, which is useful for fuzzy controller and artificial neural networks. The proposed two-side search for a rank-order finding greatly improves the response time. An experimental chip was fabricated using a 0.5-mum CMOS technology. The results of HSPICE post-layout simulation show that the response time of this circuit is approximate to 700 ns for each rank-order operation, that the input dynamic range is about 5 muA to 30 muA, and that the resolution is 1 muA for 3.3 V supply voltage.
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页码：389 / 394
页数：6
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