Damascene metal gate for 70nm CMOS process

被引:0
|
作者
Guillaumot, B [1 ]
Ducroquet, F [1 ]
Ernst, T [1 ]
Guegan, G [1 ]
Galon, C [1 ]
Renard, C [1 ]
Prévitali, B [1 ]
Rivoire, M [1 ]
Nier, ME [1 ]
Tedesco, S [1 ]
Fargeot, T [1 ]
Achard, H [1 ]
Deleopibus, S [1 ]
机构
[1] CEA, LETI, DTS, F-38054 Grenoble, France
来源
SEMICONDUCTOR SILICON 2002, VOLS 1 AND 2 | 2002年 / 2002卷 / 02期
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:793 / 802
页数:10
相关论文
共 50 条
  • [1] Advanced al damascene process for fine trench under 70nm design rule
    Han, SH
    Choi, K
    Yun, S
    Park, JH
    Lee, WS
    Lee, SW
    Choi, GH
    Hong, CK
    Kim, ST
    Chung, U
    Moon, JT
    Ryu, B
    Materials, Technology and Reliability of Advanced Interconnects-2005, 2005, 863 : 233 - 238
  • [2] 高性能70nm CMOS器件(英文)
    徐秋霞
    钱鹤
    殷华湘
    贾林
    季红浩
    陈宝钦
    朱亚江
    刘明
    半导体学报, 2001, (02) : 134 - 139
  • [3] High performance 70nm Gate Length Germanium-On-Insulator pMOSFET With High- /Metal Gate
    Romanjek, K.
    Hutin, L.
    Le Royer, C.
    Pouydebasque, A.
    Jaud, M. -A.
    Tabone, C.
    Augendre, E.
    Sanchez, L.
    Hartmann, J. -M.
    Grampeix, H.
    Mazzocchi, V.
    Soliveres, S.
    Truche, R.
    Clavelier, L.
    Scheiblin, P.
    Garros, X.
    Reimbold, G.
    Vinet, M.
    Boulanger, F.
    Deleonibus, S.
    ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2008, : 75 - 78
  • [4] A novel dram cell design and process for 70nm generation
    Chung, C. H.
    Chien, T.
    Hsiao, J. S.
    Chu, C. H.
    Kuo, W. S.
    Cheng, C. C.
    Li, F.
    Nieh, S.
    Wu, S.
    Wang, B.
    Wang, C.
    Hu, T.
    Hsiao, G.
    Che, M.
    Hon, R. Y.
    Chen, H. M.
    Chou, G.
    Chang, G.
    Chou, L.
    Shu, H. C.
    Huang, K. Y.
    Tsai, V.
    2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 101 - +
  • [5] 75nm damascene metal gate and High-k integration for advanced CMOS devices
    Guillaumot, B
    Garros, X
    Lime, F
    Oshima, K
    Tavel, B
    Chroboczek, JA
    Masson, P
    Truche, R
    Papon, AM
    Martin, F
    Damlencourt, JF
    Maitrejean, S
    Rivoire, M
    Leroux, C
    Cristoloveanu, S
    Ghibaudo, G
    Autran, JL
    Skotnicki, T
    Deleonibus, S
    INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 355 - 358
  • [6] A D-Band Monolithic Doubler in 70nm GaAs mHEMT Process
    Wen, Jincai
    Sun, Lingling
    Wang, Long
    Wu, Ting
    Liu, Jun
    2017 17TH IEEE INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY (ICCT 2017), 2017, : 1070 - 1073
  • [7] CMP-less Planarization Technology with SOG/LTO Etchback for Low Cost 70nm Gate-Last Process
    Yin, Huaxiang
    Men, Lingkuan
    Yang, Tao
    Xu, Gaobo
    Xu, Qiuxia
    Zhao, Chao
    Chen, Dapeng
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011), 2011, 34 (01): : 749 - 754
  • [8] Aberration control for 70nm optical lithography
    Sewell, H
    McClay, J
    Guzman, A
    Lafiandra, C
    LITHOGRAPHY FOR SEMICONDUCTOR MANUFACTURING II, 2001, 4404 : 279 - 289
  • [9] 157nm lithography for 70nm technology node
    Itani, T
    MICROPROCESSES AND NANOTECHNOLOGY 2001, DIGEST OF PAPERS, 2001, : 306 - 307
  • [10] Damascene metal gate technology
    Nakajima, K
    Akasaka, Y
    Saito, T
    Matsuo, K
    Yagishita, A
    Suguro, K
    ADVANCED METALLIZATION CONFERENCE 2000 (AMC 2000), 2001, : 529 - 534