The Advantages of Nanoimprint Lithography for Semiconductor Device Manufacturing

被引:6
|
作者
Asano, Toshiya [1 ]
Sakai, Keita [1 ]
Yamamoto, Kiyohito [1 ]
Hiura, Hiromi [1 ]
Nakayama, Takahiro [1 ]
Hayashi, Tomohiko [1 ]
Takabayashi, Yukio [1 ]
Iwanaga, Takehiko [1 ]
Resnick, Douglas J. [2 ]
机构
[1] Canon Inc, 20-2 Kiyohara Kogyodanchi, Utsunomiya, Tochigi 3213292, Japan
[2] Canon Nanotechnol Inc, 1807 West Braker Lane,Bldg C-300, Austin, TX 78758 USA
关键词
nanoimprint lithography; NIL; resolution; linewidth roughness; design freedom; mask life; CoO; STEP;
D O I
10.1117/12.2532522
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.
引用
收藏
页数:10
相关论文
共 50 条
  • [1] The Advantages of Nanoimprint Lithography for Semiconductor Device Manufacturing
    Sakai, Keita
    Yamamoto, Kiyohito
    Hiura, Hiromi
    Nakayama, Takahiro
    Asano, Toshiya
    Hayashi, Tomohiko
    Takabayashi, Yukio
    Iwanaga, Takehiko
    Resnick, Douglas J.
    [J]. NOVEL PATTERNING TECHNOLOGIES FOR SEMICONDUCTORS, MEMS/NEMS, AND MOEMS 2019, 2019, 10958
  • [2] High Volume Semiconductor Manufacturing using Nanoimprint Lithography
    Hamaya, Zenichi
    Seki, Junichi
    Asano, Toshiya
    Sakai, Keita
    Aghili, Ali
    Mizuno, Makoto
    Choi, Jin
    Jones, Chris
    [J]. PHOTOMASK TECHNOLOGY 2018, 2018, 10810
  • [3] High Volume Semiconductor Manufacturing Using Nanoimprint Lithography
    Takabayashi, Yukio
    Iwanaga, Takehiko
    Hiura, Mitsuru
    Morohoshi, Hiroshi
    Hayashi, Tatsuya
    Komaki, Takamitsu
    Morimoto, Osamu
    Sakai, Keita
    Zhang, Wei
    Cherala, Anshuman
    Im, Se-Hyuk
    Meissl, Mario
    Choi, Jin
    [J]. 2020 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2020), 2020,
  • [4] HIGH VOLUME SEMICONDUCTOR MANUFACTURING USING NANOIMPRINT LITHOGRAPHY
    Sakai, Keita
    [J]. 2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2019,
  • [5] The Status of Nanoimprint Lithography for High Volume Semiconductor Manufacturing
    Choi, Jin
    Resnick, Douglas J.
    [J]. JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY, 2019, 32 (05) : 753 - 757
  • [6] Nanoimprint Lithography Materials Development for Semiconductor Device Fabrication
    Costner, Elizabeth A.
    Lin, Michael W.
    Jen, Wei-Lun
    Willson, C. Grant
    [J]. ANNUAL REVIEW OF MATERIALS RESEARCH, 2009, 39 : 155 - 180
  • [7] NILCom® -: Commercialization of Nanoimprint Lithography -: Nanoimprint Lithography beyond semiconductor
    Luesebrink, H
    Glinsner, T
    Hangweier, P
    [J]. Nanofair 2005: New Ideas for Industry, 2005, 1920 : 287 - 292
  • [8] Improved Particle Control for High Volume Semiconductor Manufacturing for Nanoimprint Lithography
    Arai, Tsuyoshi
    Matsuoka, Yoichi
    Azuma, Hisanobu
    [J]. PHOTOMASK JAPAN 2018: XXV SYMPOSIUM ON PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY, 2018, 10807
  • [9] Technology review and assessment of nanoimprint lithography for semiconductor and patterned media manufacturing
    Malloy, Matt
    Litt, Lloyd C.
    [J]. JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2011, 10 (03):
  • [10] Improved Particle Control for High Volume Semiconductor Manufacturing for Nanoimprint Lithography
    Yonekawa, Masami
    Nakayama, Takahiro
    Nakagawa, Kazuki
    Maeda, Toshihiro
    Matsuoka, Yoichi
    Emoto, Keiji
    Azuma, Hisanobu
    Takabayashi, Yukio
    Aghili, Ali
    Mizuno, Makoto
    Choi, Jin
    Jones, Chris E.
    [J]. PHOTOMASK JAPAN 2017: XXIV SYMPOSIUM ON PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY, 2017, 10454