Improved Particle Control for High Volume Semiconductor Manufacturing for Nanoimprint Lithography

被引:4
|
作者
Arai, Tsuyoshi [1 ]
Matsuoka, Yoichi [1 ]
Azuma, Hisanobu [1 ]
机构
[1] Canon Inc, 20-2 Kiyohara Kogyodanchi, Utsunomiya, Tochigi 3213292, Japan
关键词
nanoimprint lithography; NIL; FPA-1200NZ2C; mask life; particle; defect; STEP;
D O I
10.1117/12.2500482
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. The NIL process involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. In this work, methods including in-situ particle removal, mask neutralization and resist filtration are discussed in detail. As a result of these methods, along with already developed techniques, particle counts on a wafer were reduced to only 0.0005 pieces per wafer path or a single particle over 2000 wafers, with a next target of 0.0001 pieces per wafer path. Particle adder reduction correlates directly with mask life, and a mask life of 81 lots (about 2000 wafers) is demonstrated. New methods are now under development to further extend mask and reduce cost of ownership. In this work on-tool wafer inspection and mask cleaning methods are also introduced.
引用
收藏
页数:8
相关论文
共 50 条
  • [1] Improved Particle Control for High Volume Semiconductor Manufacturing for Nanoimprint Lithography
    Yonekawa, Masami
    Nakayama, Takahiro
    Nakagawa, Kazuki
    Maeda, Toshihiro
    Matsuoka, Yoichi
    Emoto, Keiji
    Azuma, Hisanobu
    Takabayashi, Yukio
    Aghili, Ali
    Mizuno, Makoto
    Choi, Jin
    Jones, Chris E.
    [J]. PHOTOMASK JAPAN 2017: XXIV SYMPOSIUM ON PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY, 2017, 10454
  • [2] Improved Defectivity and Particle Control for Nanoimprint Lithography High-Volume Semiconductor Manufacturing
    Nakayama, Takahiro
    Yonekawa, Masami
    Matsuoka, Yoichi
    Azuma, Hisanobu
    Takabayashi, Yukio
    Aghili, Ali
    Mizuno, Makoto
    Choi, Jin
    Jones, Chris E.
    [J]. EMERGING PATTERNING TECHNOLOGIES, 2017, 10144
  • [3] High Volume Semiconductor Manufacturing using Nanoimprint Lithography
    Hamaya, Zenichi
    Seki, Junichi
    Asano, Toshiya
    Sakai, Keita
    Aghili, Ali
    Mizuno, Makoto
    Choi, Jin
    Jones, Chris
    [J]. PHOTOMASK TECHNOLOGY 2018, 2018, 10810
  • [4] High Volume Semiconductor Manufacturing Using Nanoimprint Lithography
    Takabayashi, Yukio
    Iwanaga, Takehiko
    Hiura, Mitsuru
    Morohoshi, Hiroshi
    Hayashi, Tatsuya
    Komaki, Takamitsu
    Morimoto, Osamu
    Sakai, Keita
    Zhang, Wei
    Cherala, Anshuman
    Im, Se-Hyuk
    Meissl, Mario
    Choi, Jin
    [J]. 2020 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2020), 2020,
  • [5] HIGH VOLUME SEMICONDUCTOR MANUFACTURING USING NANOIMPRINT LITHOGRAPHY
    Sakai, Keita
    [J]. 2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2019,
  • [6] The Status of Nanoimprint Lithography for High Volume Semiconductor Manufacturing
    Choi, Jin
    Resnick, Douglas J.
    [J]. JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY, 2019, 32 (05) : 753 - 757
  • [7] The Advantages of Nanoimprint Lithography for Semiconductor Device Manufacturing
    Sakai, Keita
    Yamamoto, Kiyohito
    Hiura, Hiromi
    Nakayama, Takahiro
    Asano, Toshiya
    Hayashi, Tomohiko
    Takabayashi, Yukio
    Iwanaga, Takehiko
    Resnick, Douglas J.
    [J]. NOVEL PATTERNING TECHNOLOGIES FOR SEMICONDUCTORS, MEMS/NEMS, AND MOEMS 2019, 2019, 10958
  • [8] The Advantages of Nanoimprint Lithography for Semiconductor Device Manufacturing
    Asano, Toshiya
    Sakai, Keita
    Yamamoto, Kiyohito
    Hiura, Hiromi
    Nakayama, Takahiro
    Hayashi, Tomohiko
    Takabayashi, Yukio
    Iwanaga, Takehiko
    Resnick, Douglas J.
    [J]. XXVI SYMPOSIUM ON PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY (PHOTOMASK JAPAN 2019), 2019, 11178
  • [9] Patterning, Mask Life, Throughput and Overlay Improvements for High Volume Semiconductor Manufacturing using Nanoimprint Lithography
    Morimoto, Osamu
    Iwanaga, Takehiko
    Takabayashi, Yukio
    Sakai, Keita
    Zhang, Wei
    Cherala, Anshuman
    Im, Se-Hyuk
    Meissl, Mario
    Choi, Jin
    [J]. PHOTOMASK TECHNOLOGY 2019, 2019, 11148
  • [10] Nanoimprint System Development and Status for High Volume Semiconductor Manufacturing
    Iwamoto, Kazunori
    Iwanaga, Takehiko
    Sreenivasan, S. V.
    Iwasa, Junji
    [J]. PHOTOMASK TECHNOLOGY 2015, 2015, 9635