Introducing a Performance Model for Bandwidth-Limited Loop Kernels

被引：0

作者：

Treibig, Jan ^{[1
]}

Hager, Georg ^{[1
]}

机构：

[1] Univ Erlangen Nurnberg, Reg Rechenzentrum Erlangen, D-8520 Erlangen, Germany

来源：

PARALLEL PROCESSING AND APPLIED MATHEMATICS, PT I | 2010年 / 6067卷

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a diagnostic performance model for bandwid-limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model.

引用

页码：615 / 624

页数：10

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