Path delay testing: Variable-clock versus rated-clock

被引:0
|
作者
Majumder, S [1 ]
Agrawal, VD [1 ]
Bushnell, ML [1 ]
机构
[1] Rutgers State Univ, Dept ECE, Piscataway, NJ 08855 USA
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-elect method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection.
引用
收藏
页码:470 / 475
页数:6
相关论文
共 25 条
  • [1] A rated-clock test method for path delay faults
    Bose, S
    Agrawal, P
    Agrawal, VD
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1998, 6 (02) : 323 - 331
  • [2] On variable clock methods for path delay testing of sequential circuits
    Chakraborty, TJ
    Agrawal, VD
    Bushnell, ML
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (11) : 1237 - 1249
  • [3] VariPipe: Low-overhead Variable-clock Synchronous Pipelines
    Toosizadeh, Navid
    Zaky, Safwat G.
    Zhu, Jianwen
    2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2009, : 117 - 124
  • [4] Online Testing of Clock Delay Faults in a Clock Network
    Chu, Wei
    Huang, Shi-Yu
    2019 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2019), 2019, : 163 - 168
  • [5] Enhancement of Clock Delay Faults Testing
    Higami, Yoshinobu
    Takahashi, Hiroshi
    Kobayashi, Shin-ya
    Saluja, Kewal K.
    2011 16TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2011, : 216 - 216
  • [6] Testing of Small Delay Faults in a Clock Network
    Yang, Shao-Fu
    Huang, Shi-Yu
    Tsai, Kun-Han
    Cheng, Wu-Tung
    2016 21TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2016,
  • [7] Delay testing with clock control: An alternative to enhanced scan
    Tekumalla, RC
    Menon, PR
    ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 454 - 462
  • [8] Delay Attack versus Clock Synchronization - A Time Chase
    Lisova, Elena
    Uhlemann, Elisabeth
    Akerberg, Johan
    Bjorkman, Mats
    2017 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), 2017, : 1136 - 1141
  • [9] Circuit and Methodology for Testing Small Delay Faults in the Clock Network
    Yang, Shao-Fu
    Wen, Zhi-Yuan
    Huang, Shi-Yu
    Tsai, Kun-Han
    Cheng, Wu-Tung
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (10) : 2087 - 2097
  • [10] Security camera based on a single chip solution using a sharply outlined display algorithm and variable-clock video encoder
    Kim, J
    Ha, J
    Jeong, S
    Yang, H
    Kang, B
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2006, 52 (01) : 292 - 297