Parasitic Resistance Modeling and Optimization for 10nm-node FinFET

被引:0
|
作者
Duan, Xicheng [1 ]
Lu, Peng [1 ]
Li, Weicong [1 ]
Woo, Jason C. S. [1 ]
机构
[1] Univ Calif Los Angeles, Dept Elect & Comp Engn, Los Angeles, CA 90095 USA
来源
2018 18TH INTERNATIONAL WORKSHOP ON JUNCTION TECHNOLOGY (IWJT) | 2018年
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
A TCAD-based study on the parasitic resistance (R-parasitics) of 10nm FinFET is perfolined. A total parasitic resistance of 1490 Omega/Fin is extracted using calibrated physical models, and the components of the R-parasitics are evaluated. It is observed that by introducing wraparound contact and highly doped source/drain, contact resistance (R-contact) of lOnm FinFET is well minimized and current crowding in the fin is suppressed. It is also found that the resistance of the lightly doped spacer region (R-spacer) constitutes more than 50% of total R-parasitics and can be optimized by introducing highly doped segments. With the optimized doping profile in the spacer, drain current (I-D) and intrinsic gain (A(V)) can be improved by 11% and 16%, respectively. In the case for 7nm-node FinFET, it was concluded that further R-contact reduction is also needed to optimize its perfounance.
引用
收藏
页码:107 / 110
页数:4
相关论文
共 50 条
  • [31] A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization
    Song, Taejoong
    Rim, Woojin
    Park, Sunghyun
    Kim, Yongho
    Yang, Giyong
    Kim, Hoonki
    Baek, Sanghoon
    Jung, Jonghoon
    Kwon, Bongjae
    Cho, Sungwee
    Jung, Hyuntaek
    Choo, Yongjae
    Choi, Jaeseung
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (01) : 240 - 249
  • [32] FINFET TECHNOLOGY: OVERVIEW AND STATUS AT 14NM NODE AND BEYOND
    Chi, Min-hwa
    2016 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2016,
  • [33] Negative Capacitance Enables FinFET and FDSOI Scaling to 2 nm Node
    Vita Pi-Ho Hu
    Pin-Chieh Chiu
    Sachid, Angada B.
    Hu, Chenming
    2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
  • [34] FinFET based SRAM bitcell design for 32 nm node and below
    Song, S. C.
    Abu-Rahma, M.
    Yeap, G.
    MICROELECTRONICS JOURNAL, 2011, 42 (03) : 520 - 526
  • [35] DSA patterning options for FinFET formation at 7nm node
    Liu, Chi-Chun
    Franke, Elliott
    Lie, Fee Li
    Sieg, Stuart
    Tsai, Hsinyu
    Lai, Kafai
    Hoa Truong
    Farrell, Richard
    Somervell, Mark
    Sanders, Daniel
    Felix, Nelson
    Guillorn, Michael
    Burns, Sean
    Hetzer, David
    Ko, Akiteru
    Arnold, John
    Colburn, Matthew
    ALTERNATIVE LITHOGRAPHIC TECHNOLOGIES VIII, 2016, 9777
  • [36] Hybrid OPC modeling with SEM contour technique for 10 nm node process
    Hitomi, Keiichiro
    Halle, Scott
    Miller, Marshal
    Graur, Ioana
    Saulnier, Nicole
    Dunn, Derren
    Okai, Nobuhiro
    Hotta, Shoji
    Yamaguchi, Atsuko
    Komuro, Hitoshi
    Ishimoto, Toru
    Koshihara, Shunsuke
    Hojo, Yutaka
    OPTICAL MICROLITHOGRAPHY XXVII, 2014, 9052
  • [37] Optimization of Leakage Current Suppression for Super Steep Retrograde Well (SSRW) 5nm-node FinFET Technology
    Kurniawan, Erry Dwi
    Du, Yan-Ting
    Wu, Yung-Chun
    Lin, Yu-Hsien
    2018 INTERNATIONAL CONFERENCE ON RADAR, ANTENNA, MICROWAVE, ELECTRONICS, AND TELECOMMUNICATIONS (ICRAMET), 2018, : 104 - 107
  • [38] Modeling Logic Error Single-Event Cross Sections at the 7-nm Bulk FinFET Technology Node
    Xiong, Yoni
    Feeley, Alexandra T.
    Ball, Dennis R.
    Bhuva, Bharat L.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2022, 69 (03) : 422 - 428
  • [39] Impact of Interface Traps and Parasitic Capacitance on Gate Capacitance of In0.53Ga0.47As-FinFET for sub 14nm Technology Node
    Pathak, Jay
    Darji, Anand
    INTERNATIONAL JOURNAL OF NANOELECTRONICS AND MATERIALS, 2019, 12 (03): : 319 - 328
  • [40] Air Spacer for 10nm FinFET CMOS and Beyond
    Cheng, K.
    Park, C.
    Yeung, C.
    Nguyen, S.
    Zhang, J.
    Miao, X.
    Wang, M.
    Mehta, S.
    Li, J.
    Surisetty, C.
    Muthinti, R.
    Liu, Z.
    Tang, H.
    Tsai, S.
    Yamashita, T.
    Bu, H.
    Divakaruni, R.
    2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,