Capacitorless dynamic random access memory cell with highly scalable surrounding gate structure

We propose the surrounding gate metal oxide semiconductor field effect transistor (MOSFET) with vertical channel [surrounding gate and vertical channel (SGVC) cell] as a one transistor (IT) dynamic random access memory (DRAM) cell. To confirm the memory operation of the SGVC cell, we fabricated a highly scalable SGVC cell. Because of its vertical channel structure and common source architecture, it can readily be made into a 4F(2) cell array. The sensing margin was around 6 mu A which is sufficiently large for read operation. Read retention time was about 4 ms meaning that the read operation is non-destructive. Also, we have revealed that not only an increase in the Volume of the floating body region but also an adequate amount of charge is required for an increase in the sensing margin,