FPGA-based Emulation of Sequential Least Squares for Coefficient Extraction of RF Power Amplifiers

被引：0

作者：

Allende Chavez, E. ^{[1
]}

Cardenas-Valdez, J. R. ^{[1
]}

Bonilla-Rodriguez, A. ^{[2
]}

Entrambasaguas-Leon, G. ^{[2
]}

Serrato-Andrade, R. Y. ^{[2
]}

Galaviz-Aguilar, J. A. ^{[2
]}

Nunez-Perez, J. C. ^{[2
]}

机构：

[1] Inst Tecnol Tijuana, Tecnol Nacl Mexico, Dept Ingn Elect & Elect, Tijuana 22500, Baja California, Mexico

[2] Inst Politecn Nacl, IPN CITEDI, Tijuana 22435, Baja California, Mexico

来源：

2018 INTERNATIONAL CONFERENCE ON MECHATRONICS, ELECTRONICS AND AUTOMOTIVE ENGINEERING (ICMEAE 2018) | 2018年

关键词：

FPGA; Memory Polynomial Model; Power Amplifier; SLS; VHDL; DIGITAL PRE-DISTORTION;

D O I：

10.1109/ICMEAE.2018.00039

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The present paper shows the full design and implementation in VHDL code of the sequential least squares algorithm to obtain the coefficients of the memory polynomial model. This model was selected to perform the behavioral modeling of power amplifiers for RF. Two main parts make up the design: a memory polynomial model with unit coefficients block and a sequential least squares calculation block. The design allows the extraction of the coefficients by providing only an input and an output of the power amplifier and makes the model more accurate with each iteration, it works with complex values which makes it possible modeling the amplitude-amplitude and amplitude-phase curves in a single model. The implementation was made through the Stratix IV DSP-FPGA development board and tested using 65,536 samples from a power amplifier NXP 10W measured at 2 GHz, achieving, an NMSE of -19.6884 dB.

引用

页码：171 / 176

页数：6

共 50 条

[11] Timing analysis with FPGA-based emulation systems
Janzen, N
Rammig, FJ
SIMULATION IN INDUSTRY: 9TH EUROPEAN SIMULATION SYMPOSIUM 1997, 1997, : 547 - 551
[12] An FPGA-based Hybrid Memory Emulation System
Wen, Fei
Qin, Mian
Gratz, Paul
Reddy, Narasimha
2021 31ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2021), 2021, : 190 - 196
[13] Design of an FPGA-based RF link for data and power transfer
Yeary, M. B.
Zhang, W.
Alkhouli, O.
Wong-Hagen, Kelly
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2006, 55 (06) : 2313 - 2319
[14] A FPGA based digital predistorter for RF power amplifiers with memory effects
Cesari, Albert
Gilabert, Pere L.
Bertran, Eduard
Montoro, Gabriel
Dilhac, Jean M.
2007 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE, VOLS 1 AND 2, 2007, : 512 - +
[15] An FPGA-based Platform for Non Volatile Memory Emulation
Lee, Taemin
Yoo, Sungjoo
2017 IEEE 6TH NON-VOLATILE MEMORY SYSTEMS AND APPLICATIONS SYMPOSIUM (NVMSA 2017), 2017,
[16] Challenges in Large FPGA-based Logic Emulation Systems
Hung, William N. N.
Sun, Richard
PROCEEDINGS OF THE 2018 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN (ISPD'18), 2018, : 26 - 33
[17] An FPGA-based hardware emulator for fast fault emulation
Hong, JH
Hwang, SA
Wu, CW
PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 345 - 348
[18] FNOCEE: A Framework for NoC Evaluation by FPGA-based Emulation
Pfefferkorn, Daniel
Schmider, Achim
Paya-Vaya, Guillermo
Neuenhahn, Martin
Blume, Holger
PROCEEDINGS INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS - ARCHITECTURES, MODELING AND SIMULATION (SAMOS XV), 2015, : 86 - 95
[19] Special Session on "FPGA-based Emulation of Hardware Architectures"
Blume, Holger
2012 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS (SAMOS): ARCHITECTURES, MODELING AND SIMULATION, 2012, : 276 - 276
[20] SSDe: FPGA-based SSD Express Emulation Framework
Lu, Yizhen
Yu, Luyang
Chen, Deming
2023 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, ICCAD, 2023,

← 1 2 3 4 5 →