Full adder operation based on Si nanodot array device

被引：0

作者：

Kaizawa, Takuya ^{[1
]}

Arita, Masashi ^{[1
]}

Fujiwara, Akira ^{[2
]}

Yamazaki, Kenji ^{[2
]}

Ono, Yukinori ^{[2
]}

Inokawa, Hiroshi ^{[3
]}

Takahashi, Yasuo ^{[1
]}

机构：

[1] Hokkaido Univ, Dept Informat Sci & Technol, Sapporo, Hokkaido 0600814, Japan

[2] NTT Corp, NTT Basic Res Labs, Atsugi, Kanagawa 2430198, Japan

[3] Shizuoka Univ, Inst Res Elect, Hamamatsu, Shizuoka 4328011, Japan

来源：

2008 IEEE SILICON NANOELECTRONICS WORKSHOP | 2008年

基金：

日本学术振兴会;

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

引用

页码：30 / 31

页数：2

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