Gate-overlapped lightly doped drain poly-Si thin film transistors by employing low-temperature doping techniques

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin film transistor (poly-Si TFT) applicable for large area AMLCD by employing the large area-and low-temperature-doping techniques, such as ion shower doping and in-situ doping. Experimental results show that the leakage current of the proposed TFTs is reduced by more than the magnitude of two orders, compared with that of conventional non-offset TFT, while the ON current is scarcely decreased. The degradation phenomena after gate bias stress in GO-LDD TFTs with in-situ doping has not been found because the electron trapping into the overlayer may be suppressed effectively by the high quality TEOS interlayer.