Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

被引：33

作者：

Huang, Zhangcai ^{[1
,2
]}

Kurokawa, Atsushi ^{[3
]}

Hashimoto, Masanori ^{[4
]}

Sato, Takashi ^{[5
]}

Jiang, Minglu ^{[6
]}

Inoue, Yasuaki ^{[6
]}

机构：

[1] Fukuoka Ind Sci & Technol Fdn, Fukuoka 8140001, Japan

[2] Waseda Univ, Res Ctr Informat Prod & Syst, Kitakyushu, Fukuoka 8080135, Japan

[3] Sanyo Elect Co Ltd, Gifu 5030195, Japan

[4] Osaka Univ, Dept Informat Syst Engn, Grad Sch Informat Sci & Technol, Suita, Osaka 5650871, Japan

[5] Kyoto Univ, Grad Sch Informat, Kyoto 6068501, Japan

[6] Waseda Univ, Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka 8080135, Japan

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2010年 / 29卷 / 02期

关键词：

CMOS inverter; gate delay; nanometer technology; overshooting time; switch-resistor model; timing analysis; SUBMICRON CMOS; CIRCUITS; GATES;

D O I：

10.1109/TCAD.2009.2035539

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the scaling of complementary metal-oxidesemiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

引用

页码：250 / 260

页数：11

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