Design a PLL for a specific loop bandwidth

被引：0
|
作者：
Holladay, K
机构：
来源：
EDN | 2000年 / 45卷 / 21期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：173 / +
页数：3
相关论文
共 50 条
  • [21] AN ESTIMATOR-PREDICTOR APPROACH TO PLL LOOP FILTER DESIGN
    STATMAN, JI
    HURD, WJ
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1990, 38 (10) : 1667 - 1668
  • [22] A design of compact PLL with adaptive active loop filter circuit
    Dosho, S
    Yanagisawa, N
    Toyama, M
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (06): : 949 - 955
  • [23] A Study on Using Pulse Generators to Design a Ring-VCO based Bang-Bang PLL/CDR with a Consistent Loop Bandwidth
    Bae, Woorham
    Jeong, Deog-Kyoon
    2014 International Conference on Electronics, Information and Communications (ICEIC), 2014,
  • [24] A 3.45-4.22 GHz PLL Frequency Synthesizer with Constant Loop Bandwidth for WLAN Applications
    Liu, Xiaolong
    Zhang, Lei
    Zhang, Li
    Wang, Yan
    Yu, Zhiping
    2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2014, : 749 - 752
  • [25] A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement
    Nagasue, Reo
    Mizuno, Isamu
    Kishida, Ryo
    Iwata, Tatsuya
    Yoshikawa, Takefumi
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
  • [26] A fully integrated 48-GHz low-noise PLL with a constant loop bandwidth
    Herzel, Frank
    Glisic, Srdjan
    Osmany, Sabbir A.
    Scheytt, J. Christoph
    Schmalz, Klaus
    Winkler, Wolfgang
    Engels, Michael
    2008 IEEE TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS, 2008, : 82 - +
  • [27] Design of a Bandwidth Limiting PLL for Grid-Tied Inverters With Guaranteed Stability
    Alexakis, Zaint A.
    Alexandridis, Antonio T.
    Papageorgiou, Panos C.
    Konstantopoulos, George C.
    IEEE TRANSACTIONS ON SUSTAINABLE ENERGY, 2025, 16 (02) : 774 - 784
  • [28] Dual-loop digital PLL design for adaptive clock recovery
    Kim, TH
    Kim, B
    PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98, 1998, : 347 - 352
  • [29] Dual-loop digital PLL design for adaptive clock recovery
    Kim, TH
    Kim, B
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1998, E81A (12) : 2509 - 2514
  • [30] Design of fast lock-in PLL with variable loop parameter control
    Hachiyama, Kazuhiro
    Nakashi, Kenichi
    Yoshizawa, Hiroyasu
    Taniguchi, Kenji
    Research Reports on Information Science and Electrical Engineering of Kyushu University, 2000, 5 (01): : 147 - 152
12345