Sub-Sampling PLL Techniques

被引：0

作者：

Gao, Xiang ^{[1
]}

Klumperink, Eric ^{[2
]}

Nauta, Bram ^{[2
]}

机构：

[1] Marvell, Santa Clara, CA USA

[2] Univ Twente, POB 217, NL-7500 AE Enschede, Netherlands

来源：

2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2015年

关键词：

Clock generation; clock multiplier; frequency multiplication; frequency synthesizer; phase locked loop; low jitter; low phase noise; low power; sub-sampling phase detector; sub-sampling PLL; PLL FOM; LOCKED LOOP; PHASE; NOISE; DETECTOR; SPUR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N-2, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-hand phase noise and limits the achievable PLL jitter.power Figure-Of-Merit (FOM). A sub sampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N-2, and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures.

引用

页数：8

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