High-Performance Noise Tolerant Comparator Design for Arithmetic Circuits

This paper presents a low power noise tolerant comparator design for arithmetic circuits. Instead of using domino logic, this paper uses a modified domino logic style. This logic uses semi-domino logic style and some extra footer transistors which lead to minimize power dissipation and noise of the comparator. The new comparator is compared with the basic domino comparator in terms of noise tolerance, delay, power consumption and power-delay product. Simulation results show the advantage of proposed comparator on the basic domino comparator in terms of noise, delay, power consumption and power-delay product. The performance of both the comparator circuits are based on UMC 180nm CMOS process models with a supply voltage of 1.8V evaluated by the comparing of the simulation results obtained from Cadence specter. From the simulation results, it can be seen clearly that the proposed comparator is quite faster, low power consuming and more noise tolerant than the basic domino comparator.