Transistor Sizing Strategy for Simultaneous Energy - Delay Optimization in CMOS Buffers

In this work, a systematic transistor sizing strategy is proposed to meet an arbitrary energy-delay target in CMOS buffers, as defined by the considered applications. This is particularly important in VLSI systems, as buffers driving large capacitive loads consume a very large energy compared to other logic gates. To this aim, an analytical and technology-independent model was first developed to find optimal circuit design parameters (e.g., sizing, number of stages). To assure true optimality, general Variable-stage effort Tapered Buffers (VTB) are considered, as opposed to Fixed-stage effort Tapered Buffers (FTB). Results show that optimized VTBs reduce energy by as much as 30%, compared to FTBs. Under balanced energy and delay, VTBs achieve 10-20% energy saving with nearly the same performance as FTBs. The adopted models and design guidelines are shown to agree well with circuit simulations in 28 and 65nm CMOS across the voltage range from 0.6 V to 1 V. This design strategy is a useful tool for circuit designers to systematically manage the energy-delay tradeoff of CMOS buffers in a simple and technology-agnostic manner.