Design of MOS-translinear multiplier/dividers in analog VLSI

被引：14

作者：

Lopez-Martin, AJ ^{[1
]}

Carlosena, A ^{[1
]}

机构：

[1] Publ Univ Navarra, Dept Elect & Elect Engn, E-31006 Pamplona, Spain

来源：

VLSI DESIGN | 2000年 / 11卷 / 04期

关键词：

analog multiplier/dividers; multipliers; MOS-translinear; voltage-translinear; CMOS analog circuits; analog VLSI;

D O I：

10.1155/2000/21852

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-mum CMOS process, are provided in order to verify the correctness of the proposed approach.

引用

页码：321 / 329

页数：9

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