In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique

被引：3

作者：

Marquez, Carlos ^{[1
,2
]}

Rodriguez, Noel ^{[1
,2
]}

Fernandez, Cristina ^{[1
,2
]}

Ohata, Akiko ^{[3
]}

Gamiz, Francisco ^{[1
,2
]}

Allibert, Frederic ^{[4
]}

Cristoloveanu, Sorin ^{[3
]}

机构：

[1] Univ Granada, Dept Elect, E-18071 Granada, Spain

[2] Univ Granada, CITIC, E-18071 Granada, Spain

[3] IMEP LAHC Minatec, F-38016 Grenoble, France

[4] Soitec SA, F-38190 Bernin, France

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2014年 / 14卷 / 03期

关键词：

Bias instability; MOSFET reliability; SOI technology; pseudo-MOSFET; TEMPERATURE INSTABILITY; NBTI DEGRADATION; TRAP GENERATION; INTERFACE; TRANSISTOR; RECOVERY;

D O I：

10.1109/TDMR.2014.2332818

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Bias instability is a reliability issue affecting the electrical characteristics of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using the pseudo-MOSFET technique. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated using measure-stress-measure and on-the-fly methods. The origin of the instability, the dependence of the degradation with time, and the recovery after the stress are discussed.

引用

页码：878 / 883

页数：6

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